A New Thread Block Scheduling Technique for Improving the Performance of GPGPU Architecture
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General-Purpose computing on Graphics Processing Units (GPGPUs) are becoming one of the most attractive computing platforms for handling high performance computing applications. This trend is more and more increasing especially with the help of new parallel programming models like CUDA and OpenCL, etc. The state-of-the-art GPGPU schedulers are likely to allocate as many as possible number of thread blocks into streaming multiprocessors. In fact, this is not always the optimal way to maximize the hardware utilization. This paper studies the drawbacks of the common-used round-robin scheduling at the thread block level. After that, we propose a new technique that can dynamically adjust the number of thread blocks to be assigned to streaming multiprocessors depending on the level of memory and interconnection network contention. Our simulation results on a 15-core GPGPU platform show that the proposed technique provides better performance over the baseline round-robin scheduling by around 6.3% on average.
Abstract
General-Purpose computing on Graphics Processing Units (GPGPUs) are becoming one of the most attractive computing platforms for handling high performance computing applications. This trend is more and more increasing especially with the help of new parallel programming models like CUDA and OpenCL, etc. The state-of-the-art GPGPU schedulers are likely to allocate as many as possible number of thread blocks into streaming multiprocessors. In fact, this is not always the optimal way to maximize the hardware utilization. This paper studies the drawbacks of the common-used round-robin scheduling at the thread block level. After that, we propose a new technique that can dynamically adjust the number of thread blocks to be assigned to streaming multiprocessors depending on the level of memory and interconnection network contention. Our simulation results on a 15-core GPGPU platform show that the proposed technique provides better performance over the baseline round-robin scheduling by around 6.3% on average.
참고문헌 (18)
- A. Bakhola, "Analyzing CUDA Workloads uisng a Detailed GPU Simulator", ISPASS (2009)
- AMD’s Fusion Finally Arrives, "K. Krewell", Microprocessor, ~ (2011)
- 김재하, "GPU 기반 테셀레이션을 이용한 연속상세단계 기법", 한국차세대컴퓨팅학회 논문지, 9(1), pp.84~92 (2013), 한국차세대컴퓨팅학회
- 이인, "디테일을 유지하는 대규모 지형의 GPU 기반 가시화 및 편집", 한국차세대컴퓨팅학회 논문지, 8(4), pp.35~46 (2012), 한국차세대컴퓨팅학회
- 윤민, "GPU를 이용한 Salsa20 스트림 암호의 병렬화", 한국차세대컴퓨팅학회 논문지, 5(1), pp.53~62 (2009), 한국차세대컴퓨팅학회
- VIDIA, "CUDA C Programming Guide", ~ (2010)
- A. Munshi, "The OpenCL Specification", ~ (2011)
- Neither More Nor Less: Optimizing Thread-Level Parallelism for GPGPUs, "O. Kayiran", PACT, ~ (2013)
- Improving GPGPU Resource Utilization Through Alternative Thread Block Scheduling, "M. Lee", HPCA, ~ (2014)
- NVIDIA’s Next Generation CUDA Compute Architecture, "NVIDIA", NVIDIA, Fermi, ~ (2011)
- NVIDIA Tegra Multiprocessor Architecture, "NVIDIA", ~ (2010)
- N. B. Lakshiminarayana, "Effect of Instruction Fetch and Memory Scheudling on GPU Performance", Workshop of Language, Compiler and Architecture Support for GPGPU (2010)
- Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow, "W. W. Fung", MICRO, ~ (2007)
- Energy-Efficient Mechanisms for Managing Thread Context in Throughput Processors, "M. Gebhart", ISCA, ~ (2011)
- Improving GPU Performance via Large Warps and Two-Level Warp Scheduling, "V. Narasiman", MICRO, ~ (2011)
- Orchestrated Scheduling and Prefetching for GPGPUs, "A. Jog", ISCA, ~ (2013)
- "CUDA GPU Computing SDK"[URL]
- NVIDIA CUDA Software and GPU Parallel Computing Architecture, "D. Kirk", ISMM, ~ (2007)