An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.
Abstract
Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.
참고문헌 (19)
- R. Micheloni, "Error Correction Codes for Non-Volatile Memories" (2008), Springer
- J. C. Moreira, "Essentials of Error–Control Coding" (2006), John Wiley and Sons
- R. G. Gallager, "Low Density Parity Check Codes", IRE Transactions on Information Theory, 8(1), pp.21~28 (1962)
- G. Dong, "On the Use of Soft-Decision Error-Correction Codes in NAND Flash Memory", IEEE Transactions on Circuits and Systems I, 58(2), pp.429~439 (2011)
- J. Kim, "Rate-0. 96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory", IEEE Transactions on Very Large Scale Integration(VLSI)Systems, 22(5), pp.1004~1015 (2014)
- Y. Cai, "Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives", Proceedings of the IEEE, 105(9), pp.1666~1704 (2017)
- R. Bez, "Introduction to Flash Memory", Proceedings of the IEEE, 91(4), pp.489~502 (2003)
- N. Mielke, "Bit Error Rate in NAND Flash Memories", 2008IEEE International Reliability Physics Symposium, pp.9~19 (2008)
- L. -P. Chang, "On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems", Proceedings of the 2007 ACM symposium on Applied computing, pp.1126~1130 (2007)
- Y. -H. Chang, "Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design", 2007 44th ACM, 2007, 212~217
- M. Murugan, "Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead", 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST) (2011)
- Y. Pan, "Error Rate-Based Wear-Leveling for Nand Flash Memory at Highly Scaled Technology Nodes", IEEE Transactions on Very Large Scale Integration(VLSI)Systems, 21(7), pp.1350~1354 (2013)
- B. Peleato, "BER-Based Wear Leveling and Bad Block Management for NAND Flash", 2015 IEEE International Conference on Communications (ICC), pp.295~300 (2015)
- X. Shi, "Program Error Rate-based Wear Leveling for NAND Flash Memory", 2018 Design, Automation and Test in Europe Conference & Exhibition (DATE), pp.1241~1246 (2018)
- M. Karimi, "On Characterization of Elementary Trapping Sets of Variable-Regular LDPC codes", IEEE Transactions on Information Theory, 60(9), pp.5188~5203 (2014)
- S. Laendner, "LDPC Codes Based on Latin Squares : Cycle Structure, Stopping Set, and Trapping Set Analysis", IEEE Transactions on Communications, 55(2), pp.303~312 (2007)
- M. P. C. Fossorier, "Quasi-Cyclic Low-Density Parity-Check Codes from Circulant Permutation Matrices", IEEE Transactions on Information Theory, 50(8), pp.1788~1793 (2004)
- C. Yoon, "Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Daigonal Parity Structure", 2007 IEEE Wireless Communications and Networking Conference, pp.663~667 (2007)
- J. Chen, "Reduced-Complexity Decoding of LDPC Codes", IEEE Transactions on Communications, 53(8), pp.1288~1299 (2005)