다중모드 센서 신호 처리 프로세서의 FPGA 기반 설계 및 구현
Design and Implementation of Multi-mode Sensor Signal Processor on FPGA Device
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초록
Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinx’s Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.
Abstract
Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinx’s Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.
참고문헌 (14)
- Y. Perwej, "An Extended Review on Internet ot Things(IoT)and its Promising Applications", Commun. Appl. Electronics(CAE), 7(26), pp.8~22 (2019), ISSN
- N. K. Suryadevara, "Wireless Sensor Network Based Home Monitoring System for Wellness Determination of Elderly", IEEE Sens. J, 12(6), pp.1965~1972 (2012)
- S. Kang, "sEMGbased Hand Gesture Recognition Using Binarized Neural Network", Sensors, 23(3), pp.1436~1451 (2023)
- M. Z. Arshad, "Gait-based Frailty Assessment using Image Representation of IMU Signals and Deep CNN", Proc. of 202143rd Annual Int. Conf. IEEE Eng. in Med. Biol. Soc. (EMBC), pp.1874~1879 (2021)
- K. Abratkiewicz, "Target Doppler Rate Estimation Based on the Complex Phase of STFT in Passive Forward Scattering Radar", Sensors, 19(16), pp.3627~3639 (2019)
- J. Heo, "FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing", Sensors, 21(19), pp.6443~6458 (2021)
- N. N. Alajlan, "TinyML : Enabling of Inference Deep Learning Models on Ultra-Low-Power IoT Edge Devices for AI Applications", Micromachines, 13(6), pp.851~872 (2022)
- V. Aivaliotis, "IoT-Based Multi-Sensor Healthcare Architectures and a LightweightBased Privacy Scheme", Sensors, 22(11), pp.4269~4279 (2022)
- M. Wang, "A pipelined areaefficient and high-speed reconfigurable processor for floating-point FFT", IFFT and DCT, Microelectronics J, pp.2016, 47[DOI]
- S. Mach, "A Transprecision Floating-point Architecture for Energy-Efficient Embedded Computing", Proc. of 2018IEEE Int. Symp. Circuits Syst. (ISCAS), pp.1~5 (2018)
- G. Tagliavini, "A Transprecision Floating-Point Platform for Ultra-Low Power Computing", Proc. of 2018 Design, Autom. Test in Eur. Conf. Exhib. (DATA), pp.1051~1056 (2018)