칩의 크기가 제한된 단일칩 프로세서를 위한 레벨 1 캐시구조
A Level One Cashe Organization for Chip-Size Limited Single Processor
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초록
이 논문에서는 단일 칩 프로세서에서 제한된 공간의 레벨 1 캐시를 구성하고 있는 선인출 캐시 와 요구인출 캐시 의 합이 일정할 때, 와 의 크기의 적정한 비율을 실험을 통하여 분석하였다. 실험 결과, 와 의 합이 16KB일 경우에는 을 12KB, 를 4KB로 구성하고 의 선인출 기법과 캐시교체정책은 각각 OBL과 FIFO을 적용시키는 레벨 1 캐시 구조가 가장 성능이 우수함을 보였다. 또한 이 분석은 와 의 합이 32KB 이상인 경우에는 의 선인출 기법으로는 동적필터 기법을 사용하는 것이 유리함을 보였고 32KB의 공간이 가용한 경우에는 을 28KB, 를 4KB로, 64KB가 가용한 경우에는 을 48KB, 를 16KB로 레벨 1 캐시를 분할하는 것이 가장 좋은 성능을 발휘함을 보였다.
Abstract
This paper measured a proper ratio of the size of demand fetch cache to that of prefetch cache by imulation when the size of and are constant which organize space-limited level 1 cache of a single microprocessor chip. The analysis of our experiment showed that in the condition of the sum of the size of and are 16 KB, the level 1 cache organization by constituting with 4 KB and employing OBL and FIFO as a prefetch technique and a cache replacement policy respectively resulted in the best performance. Also, this analysis showed that in the condition of the sum of the size of and are over 32 KB, employing dynamic filtering as prefetch technique of are more advantageous and splitting level 1 cache by constituting with 28 KB and with 4 KB in the case of 32 KB of space are available, by constituting with 48 KB and with 16 KB in the case of 64 KB elicited the best performance.
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