DIMM-in-a-PACKAGE Memory Device Technology for Mobile Applications
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A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the centerbonded devices (DDR3, DDR4 and LPDDR3 ×16 die) and for the face up wirebonded ×32 LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.
Abstract
A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the centerbonded devices (DDR3, DDR4 and LPDDR3 ×16 die) and for the face up wirebonded ×32 LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.
참고문헌 (2)
- R. Crisp, "High Performance Multi-Die DRAM Packaging for High-Speed Server Applications using Dual Face Down Architecture with Wirebond Assembly Infrastructure", The 10th International Symposium on Microelectronics and Packaging (ISMP 2011) (2011), The Korean Microelectronics and Packaging Society (KMEPS)
- U. Kang, "8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology", 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009), pp.130~ (2009), IEEE