Design Considerations of Linear Algebra Processor for Wearable Brain-Computer Interface System
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In this paper, we introduced design considerations of a wearable brain-computer interface (BCI) that performs a target identification algorithm based on linear algebra. Steady-state visual evoked potential (SSVEP) based wearable BCI have been studied to enable paralyzed patients to communicate with others. However, performance indicators such as target identification accuracy and the information transfer rate (ITR) still need to be further improved for wearable devices. This paper discusses several considerations for designing algorithms and linear algebra accelerating hardware. In the case of target identification algorithms, a signal binarization technique and candidate reduction technique which are proposed in the previous works can be considered in single-channel SSVEP-based software implementations and multi-channel SSVEP processing in hardware to reduce computational complexity, respectively. For hardware architecture design, we introduced architectural considerations of processing element array that can effectively perform various linear algebra operations.
Abstract
– In this paper, we introduced design considerations of a wearable brain-computer interface (BCI) that performs a target identification algorithm based on linear algebra. Steady-state visual evoked potential (SSVEP) based wearable BCI have been studied to enable paralyzed patients to communicate with others. However, performance indicators such as target identification accuracy and the information transfer rate (ITR) still need to be further improved for wearable devices. This paper discusses several considerations for designing algorithms and linear algebra accelerating hardware. In the case of target identification algorithms, a signal binarization technique and candidate reduction technique which are proposed in the previous works can be considered in single-channel SSVEP-based software implementations and multi-channel SSVEP processing in hardware to reduce computational complexity, respectively. For hardware architecture design, we introduced architectural considerations of processing element array that can effectively perform various linear algebra operations.
참고문헌 (15)
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