A Low Power Capacitive Interface IC with Automatic Parasitic Offset Calibration using Dual-Range Digital Servo Loop
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Capacitive sensor interfaces are widely used for various micro-electro mechanical system (MEMS), however, capacitive sensor interface circuits suffer from severe parasitic capacitance problems. The parasitic capacitance, which is generally much larger than the sensing capacitance, results the large output offset variations. Thus an additional parasitic cancellation with external calibration equipment is required. This paper presents a low power capacitive interface IC with automatic parasitic calibration using dual-range digital servo loop for capacitive micro sensors without external equipment. The output offset with few hundreds fF parasitic capacitance of the capacitive sensor interface must be canceled to measure fF capacitance. To overcome the limitations of design rule and perform the wide compensation range, this paper proposed capacitor domain compensation (coarse range compensation) and charge domain compensation (fine range compensation). The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The input parasitic capacitances in the range from -10.6 pF to +10.6 pF can be cancelled out automatically, and the required calibration time is lower than 6 ms.
Abstract
Capacitive sensor interfaces are widely used for various micro-electro mechanical system (MEMS), however, capacitive sensor interface circuits suffer from severe parasitic capacitance problems. The parasitic capacitance, which is generally much larger than the sensing capacitance, results the large output offset variations. Thus an additional parasitic cancellation with external calibration equipment is required. This paper presents a low power capacitive interface IC with automatic parasitic calibration using dual-range digital servo loop for capacitive micro sensors without external equipment. The output offset with few hundreds fF parasitic capacitance of the capacitive sensor interface must be canceled to measure fF capacitance. To overcome the limitations of design rule and perform the wide compensation range, this paper proposed capacitor domain compensation (coarse range compensation) and charge domain compensation (fine range compensation). The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The input parasitic capacitances in the range from -10.6 pF to +10.6 pF can be cancelled out automatically, and the required calibration time is lower than 6 ms.
참고문헌 (9)
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