Latch Voltage Modulation of Cryptographic Transistor for True Random Number Generator
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We propose a latch voltage modulation of a single MOSFET functioning as a single-transistor oscillator with an analog-to-digital converter (ADC) for a true random number generator (TRNG). The MOSFET generates irregularly oscillating analog signals due to a single transistor latch with latch-up voltage (VLU) and latch-down voltage (VLD), which are then converted into digitized random numbers by the ADC. To achieve a controllable TRNG, it is crucial to examine how process parameters, such as the doping concentration of the p-well (Npwell), the depth of the p-well (Tpwell), and the junction depth of the source/drain (xj), influence VLU and VLD in a single-transistor oscillator implemented on a bulk-silicon wafer (1T-Obulk). The randomly fluctuating output voltage (Vout), associated with VLU and VLD, serves as an entropy source for the TRNG. The random oscillation of Vout, generated at the drain of the 1T-Obulk, was observed in a fabricated device using the TSMC 180 nm foundry process. Since aligning Vout from a 1T-Obulk with the input voltage range of an analog-to-digital converter (ADC) is crucial, the three aforementioned major process parameters are tuned to control Vout. This approach contributes to advancing next-generation security technology.
Abstract
We propose a latch voltage modulation of a single MOSFET functioning as a single-transistor oscillator with an analog-to-digital converter (ADC) for a true random number generator (TRNG). The MOSFET generates irregularly oscillating analog signals due to a single transistor latch with latch-up voltage (VLU) and latch-down voltage (VLD), which are then converted into digitized random numbers by the ADC. To achieve a controllable TRNG, it is crucial to examine how process parameters, such as the doping concentration of the p-well (Npwell), the depth of the p-well (Tpwell), and the junction depth of the source/drain (xj), influence VLU and VLD in a single-transistor oscillator implemented on a bulk-silicon wafer (1T-Obulk). The randomly fluctuating output voltage (Vout), associated with VLU and VLD, serves as an entropy source for the TRNG. The random oscillation of Vout, generated at the drain of the 1T-Obulk, was observed in a fabricated device using the TSMC 180 nm foundry process. Since aligning Vout from a 1T-Obulk with the input voltage range of an analog-to-digital converter (ADC) is crucial, the three aforementioned major process parameters are tuned to control Vout. This approach contributes to advancing next-generation security technology.