순환중복검사 부호용 하드웨어 HDL 코드 생성기
HDL Codes Generator for Cyclic Redundancy Check Codes
1
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
전통적으로 CRC 하드웨어는 선형 되먹임 시프트 레지스터를 이용하여 한 클럭 싸이클 당 하나의 비트를 처리하는 직렬처리 방식을 사용하였다. 최근 다양한 응용 시스템에서 빠른 데이터 처리를 요구하면서 이를 만족시키기 위하여 다양한 병렬화 기법들이 제안되었고, Look-Ahead 병렬화 기법이 짧은 최대 경로 지연을 가지는 장점 덕분에 가장 널리 적용된다. 하지만 Look-Ahead 병렬 하드웨어의 경우 각 레지스터 값과 입력 데이터의 이동에 대하여 예측을 하여야 하기 때문에 직렬 하드웨어 대비 HDL 코드의 작성이 복잡하다. 따라서 본 논문에서는 다양한 CRC 다항식과 병렬화 계수를 지원할 수 있는Look-Ahead 기반의 CRC 병렬화 하드웨어 생성기를 제안한다. 생성된 HDL 코드의 합성 결과를 분석함으로써 제안된 생성기의 활용 가능성을 판단한다
Abstract
Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check(CRC) codes for a serial input. Since many applications including network and storage systems demand as highthroughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Amongvarious parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitableto consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardwaregenerator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental resultsverify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.
참고문헌 (10)
- W. W. Peterson, "Cyclic Codes for Error Detection", Proceedings of the IRE, 49, pp.228~235 (1961)
- G. Campobello, "Parallel crc realization", IEEE Transactions on Computers, 52(10), pp.1312~1319 (2003), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Jaehwan Jung, "Efficient Parallel Architecture for Linear Feedback Shift Registers", IEEE Transactions on Circuits and Systems II: Express Briefs, 62(11), pp.1068~1072 (2015), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- G. Albertengo, "Parallel CRC generation", IEEE Micro, 10(5), pp.63~71 (1990), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- E. Stavinov, "A Parallel CRC Generation Method", Circuits Celler Magzines for Computers, ~ (2010)
- T.-B. Pei, "High-speed parallel CRC circuits in VLSI", IEEE Transactions on Communications, 40(4), pp.653~657 (1992), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- M. Walma, "Pipelined Cyclic Redundancy Check (CRC) Calculation", 2007 16th International Conference on Computer Communications and Networks, pp.365~370 (2007)
- Carlo Condo, "Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE", LTE-Advanced, 2014, pp.21(11), 1380~1384[DOI]
- C. Cheng, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming", IEEE Transactions on Circuits and Systems II: Express Briefs, 53(10), pp.1017~1021 (2006), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Manohar Ayinala, "High-Speed Parallel Architectures for Linear Feedback Shift Registers", IEEE Transactions on Signal Processing, 59(9), pp.4459~4469 (2011), Institute of Electrical and Electronics Engineers (IEEE)[DOI]