PECVD와 NO 어닐링 공정을 이용하여 제작한 N-based 4H-SiC MOS Capacitor의 SiC/SiO2 계면 특성
SiC/SiO2 Interface Characteristics in N-based 4H-SiC MOS Capacitor Fabricated with PECVD and NO Annealing Processes
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초록
본 연구에서는 4H-SiC MOSFET의 주요 문제점인 SiC/SiO2 계면의 특성을 향상시키기 위해 PECVD (plasma enhanced chemical vapor deposition) 공정을 이용하여 n-based 4H-SiC MOS Capacitor를 제작하였다. 건식 산화 공정의 낮은 성장속도, 높은 계면포획 밀도와 SiO2의 낮은 항복전계 등의 문제를 극복하기 위하여 PECVD와 NO 어닐링 공정을 사용하여 MOS Capacitor를 제작하였다. 제작이 끝난 후, MOS Capacitor의 계면특성을 hi-lo C-V 측정, I-V 측정 및 SIMS를 이용해 측정하고 평가하였다. 계면의 특성을 건식 산화의 경우와 비교한 결과 20% 감소한 평탄대 전압 변화, 25% 감소한 SiO2 유효 전하 밀도, 8MV/cm의 증가한 SiO2 항복전계 및 1.57eV의 유효 에너지 장벽 높이, 전도대 아래로 0.375~0.495eV만큼 떨어져 있는 에너지 영역에서 69.05% 감소한 계면 포획 농도를 확인함으로써 향상된 계면 및 산화막 특성을 얻을 수 있었다.
Abstract
In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/SiO2 interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of SiO2, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor’s interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.
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