직접 보상 트랜지스터를 사용하는 고주파 PSR 개선LDO 레귤레이터
High-Frequency PSR-Enhanced LDO regulator Using Direct Compensation Transistor
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참고문헌
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초록
본 논문에서는 고주파 영역에서의 전원잡음제거 (PSR) 특성이 개선된 low drop-out (LDO) 레귤레이터를 제안한다. 특히,PMOS 전력 스위치의 유한한 출력저항을 관통하는 고주파 전원잡음을 상쇄하기 위해 출력저항이 큰 NMOS 트랜지스터를보상 회로로 추가하였다. 보상 트랜지스터에 의한 전원잡음제거는 해석적으로 설명하여 개선에 대한 방향을 제시하였다. 0.35μm 표준 CMOS 공정으로 회로를 제작하고 Spectre 시뮬레이션을 수행하여 10MHz에서 기존의 LDO 레귤레이터 대비26dB의 PSR 개선을 확인하였다.
Abstract
In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristicsin the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensationcircuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. Theelimination of power supply noise by the compensating transistor was explained analytically and presented as thedirection for further improvement. The circuit was fabricated in a 0.35-μm standard CMOS process and Spectersimulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at10 MHz.
참고문헌 (8)
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