저전압급 ESD 보호를 위한 NPN BJT 내장형 SCR 설계에 관한 연구
A study on the Design of NPN BJT built-in SCR for Low Voltage Class ESD Protection
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초록
본 논문에선 기존의 ESD 보호소자보다 간단한 구조의 ESD 보호소자를 제안하였다. 제안하는 새로운 구조는 N+확산영역을 추가하고 브릿지영역과 연결함으로써 추가 NPN 기생 바이폴라 트랜지스터를 동작시켜 전류이득을 낮춘다. 그 결과 제안된 ESD 보호소자는 10.8V의 트리거 전압 및 6.1V의 홀딩전압을 갖는 것을 확인하였다. 이는 5V 어플리케이션에 신뢰성을 가질 것으로 기대되며높은 감내특성을 가질 것으로 예상된다.
Abstract
In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.
참고문헌 (6)
- Albert Z, "On-Chip ESD Protection for Integrated devices" (2002), Springer
- Ming-Dou Ker, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test", IEEE Journal of Solid-State Circuits, 43(11), pp.2533~2545 (2008), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- O. Semenov, "ESD protection design for advanced CMOS", Proc. SPIE, pp.123~131 (2001)
- Yongseo Koo, "Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology", Microelectronics Journal, 40(6), pp.1007~1012 (2009), Elsevier BV[DOI]
- R. G. Wagner, "Extend and cost of EOS", ESD damage in an IC manufacturing process, ESD Symp., pp.1993[DOI]
- Ming-Dou Ker, "Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test", IEEE Journal of Solid-State Circuits, 43(11), pp.2533~2545 (2008), Institute of Electrical and Electronics Engineers (IEEE)[DOI]