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게이트 전류 감지 구조를 이용한 향상된 레귤레이션 특성의LDO regulator

LDO regulator with improved regulation characteristics using gate current sensing structure

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초록

게이트 전류 감지 구조는 LDO 레귤레이터가 오버슈트 또는 언더슈트 상황 발생 시 출력전압의 레귤레이션을 보다 효과적으로제어하기 위해 제안되었다. 기존의 전형적인 LDO 레귤레이터는 부하전류가 변화할 때 레귤레이션 전압 변화가 발생한다. 하지만게이트 전류 감지 구조를 이용하여 패스 트랜지스터에 있는 게이트 단자 전류를 공급/방전 함으로 인해 패스 트랜지스터의 동작 속도를 더욱 향상시킬 수 있다. 게이트 전류 감지 구조를 이용한 LDO 레귤레이터의 입력전압은 3.3 V ~ 4.5 V 이며 출력 전압은3 V이고 부하 전류는 최대 250 mA의 값을 갖는다. 시뮬레이션 결과, 부하 전류가 250 mA 까지 변화할 때 약 9 mV의 전압 변화값을 확인하였다.

Abstract

The gate current sensing structure was proposed to more effectively control the regulation of the output voltagewhen the LDO regulator occurs in an overshoot or undershoot situation. In a typical existing LDO regulator, theregulation voltage changes when the load current changes. However, the operation speed of the pass transistorcan be further improved by supplying/discharging the gate terminal current in the pass transistor using a gatecurrent sensing structure. The input voltage of the LDO regulator using the gate current sensing structure is 3.3 Vto 4.5 V, the output voltage is 3 V, and the load current has a maximum value of 250 mA. As a result of thesimulation, a voltage change value of about 12 mV was confirmed when the load current changed up to 250 mA.

참고문헌 (7)

  1. Amir Nakhlestani, "Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications", IEEE Transactions on Circuits and Systems II: Express Briefs, 68(2), pp.692~696 (2021), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  2. Yong-Seo Koo, "A design of low-area low drop-out regulator using body bias technique", IEICE Electronics Express, 10(19), pp.20130300~20130300 (2013), Institute of Electronics, Information and Communications Engineers (IEICE)[DOI]
  3. Xiaofei Ma, "A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization", IEEE Transactions on Circuits and Systems II: Express Briefs, 67(4), pp.725~729 (2020), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  4. Yan Lu, "A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection", IEEE Transactions on Circuits and Systems I: Regular Papers, 62(3), pp.707~716 (2015), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  5. Sang Wook Kwon, "Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications", Electronics Letters, 58(19), pp.714~716 (2022), Institution of Engineering and Technology (IET)[DOI]
  6. Sang-Wook Kwon, "Design of capacitor-less LDO regulator with SCR-based ESD protection using dual push-pull stage", International Journal of Electronics, 110(10), pp.1713~1732 (2022), Informa UK Limited[DOI]
  7. Sang-Wook Kwon, "Design of LDO Regulator With High Reliability ESD Protection Circuit Using Analog Current Switch Structure for 5-V Applications", IEEE Access, 11, pp.37472~37482 (2023), Institute of Electrical and Electronics Engineers (IEEE)[DOI]

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