LDO 레귤레이터의 파괴방지 및 효율성을 위한 ESD 보호회로 설계에 대한 연구
A Study on the Design of ESD Protection Circuit for Prevention of Destruction and Efficiency of LDO Regulator
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초록
본 논문에서는 부하전류에 따라 LDO(Low Drop Out) 레귤레이터의 효과적인 동작과 파괴 방지를 위해 ESD(Electro StaticDischarge) 보호회로를 내장한 LDO 레귤레이터를 제안한다. 제안하는 LDO 레귤레이터는 additional feedback current 회로구조를 이용하여 LDO 레귤레이터의 출력전압에 따라 더욱 효과적으로 패스 트랜지스터의 게이트 노드 전압을 조절할 수 있다. 또한 기존의 ESD 보호소자에 P+ bridge를 추가하여 SCR 루프 상의 전류 이득을 감소시켜 홀딩 전압을 약 2V 가량 높인 새로운 구조를 내장하여 ESD 상황에 대해 높은 신뢰성을 가질 것으로 예상된다.
Abstract
This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit toeffectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according tothe output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, itis expected to have high reliability for the ESD situation by embedding a new structure that increases the holdingvoltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESDprotection device.
참고문헌 (6)
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- Albert Z. H. Wang, "On-Chip ESD Protection for Integrated Circuits" (2002), Springer
- Sang-Wook Kwon, "Design of LDO Regulator With High Reliability ESD Protection Circuit Using Analog Current Switch Structure for 5-V Applications", IEEE Access, 11, pp.37472~37482 (2023), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
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