FPGA 기반 고속 템플릿 매칭 블록 설계를 통한비전 웨이퍼 얼라인먼트 시스템 구현
FPGA Design of High-speed Template Matching Block for Vision Wafer Alignment System Implementation
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본 연구에서는 비전 웨이퍼 얼라인먼트 시스템 구현을 위한 FPGA 기반 템플릿 매칭 블록 설계 기법과 그 결과를 제안한다. 현재웨이퍼에 새겨진 마커를 찾아 위치를 보정하는 소프트웨어 기반의 비전 웨이퍼 얼라인먼트 시스템의 고속화를 위해, 고해상도의 웨이퍼 이미지를 고속으로 처리하기 위한 NCC(Normalized Cross Correlation) 기반의 템플릿 매칭 알고리즘을 최적화하고 이를 FPGA를 이용하여 구현하였다. NCC 기법은 연산 복잡도가 높고 템플릿 매칭은 템플릿 이미지가 소스 이미지를 픽셀 단위로 슬라이딩하며유사도를 계산하기 때문에 긴 스캔 시간이 문제가 된다. 본 논문에서는 연산량을 줄이는 슬라이딩 윈도우 방법과 제곱근, 루트, 평균연산등의 수학 연산을 최적화하여 복잡도를 낮춘 NCC 기법을 제안하고, 이를 적용한 템플릿 매칭 블록을 FPGA로 구현하였다. 성능분석결과 부동 소수점을 갖는 SW 기반의 기존 알고리즘과 비교하여 약 99.98% 감소된 연산 복잡도를 갖음을 확인하였다
Abstract
In this study, we propose a design technique for a FPGA-based template matching block for implementing a visionwafer alignment system and its results. In order to speed up the software-based vision wafer alignment system thatfinds markers engraved on a wafer and corrects their positions, we optimized a template matching algorithm basedon NCC (Normalized Cross Correlation) for high-speed processing of high-resolution wafer images and implementedit using FPGA. The NCC technique has high computational complexity, and template matching calculates similarityby sliding the template image over the source image pixel by pixel, which causes long scan times. In this paper, wepropose an NCC technique that reduces the computational complexity by optimizing mathematical operations suchas the sliding window method and square root, root, and average operations, and implemented a template matchingblock using the technique using FPGA. The performance analysis results show that the computational complexity isreduced by approximately 99.98% compared to the existing SW-based algorithm with floating points.
참고문헌 (11)
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