컴퓨터 생성 홀로그램의 고속 생성을 위한 하드웨어 구현
Hardware Implementation for High-Speed Generation of Computer Generated Hologram
0
조회
0
다운로드
2
인용
0
참고문헌
키워드
초록
In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of 16×16 size, and it takes about 4 sec for generating a hologram of a 1,024×1,024 size, using 6K point sources.
Abstract
In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of 16×16 size, and it takes about 4 sec for generating a hologram of a 1,024×1,024 size, using 6K point sources.
참고문헌 (13)
- T. Motoki, "Present Status of Three-Dimensional Television Research", Proc. IEEE, 83(7), pp.1009~1021 (1995)
- J. K. Chung, "Three-Dimensional Holographic Imaging" (2002), John Wiley & Sons, Inc.
- P. Hariharan, "Basics of Holography" (2002), Cambridge University Press
- Mark Lucente, "Interfactive Computation of Holograms Using a Look-up Table", Journal of Electronic Imaging, 2(1), pp.28~34 (1993)
- H. Yoshikawa, "Fast Computation of Fresnel Holograms employing Differences", Proceeding of SPIE, 3956 (2000)
- T. Shimobaba, "An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition", Computer Physics Communications, 138, pp.44~52 (2001)
- T. Ito, "Special-Purpose computer HORN-5 for a real-time electroholography", Optics Express, 13(6) (2005)
- Y. Ichihashi, "HORN-6 special-purpose clustered computing system for electroholography", Optics Express, 17(16), pp.13895~13903 (2009)
- Y. -H. Seo, "An architecture of a high-speed digital hologram generator based on FPGA", Journal of Systems Architecture, 56, pp.27~37 (2009)
- 이승학, "GPU를 이용한 SDR 시스템 용 LTE MIMO 기지국 기능 구현", (사)디지털산업정보학회 논문지, 8(4), pp.91~98 (2012), (사)디지털산업정보학회
- 김태현, "SDR 시스템에서 GPU를 사용한 Lattice Reduction-aided 검출기 구현", (사)디지털산업정보학회 논문지, 7(3), pp.55~61 (2011), (사)디지털산업정보학회
- 서영호, "디지털 홀로그램의 고속 생성을 위한 병렬화 알고리즘 및 셀 기반의 하드웨어 구조", 방송공학회 논문지, 16(1), pp.54~63 (2011), 한국방송공학회
- Y. -H. Seo, "Hardware architecture of highperformance digital hologram generator on the basis of a pixel-by-pixel calculation scheme", Applied optics, 51(18), pp.4003~4012 (2012)