직접 메모리 접근 장치에서 버스트 데이터 전송 기능의 효과적인 활용
Efficient Utilization of Burst Data Transfers of DMA
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Resolving of memory access latency is one of the most important problems in modern embedded system design. Recently, tons of studies are presented to reduce and hide the access latency. Burst/page data transfer modes are representative hardware techniques for achieving such purpose. The burst data transfer capability offers an average access time reduction of more than 65 percent for an eight-word sequential transfer. However, solution of utilizing such burst data transfer to improve memory performance has not been accomplished at commercial level. Therefore, this paper presents a new technique that provides the maximum utilization of burst transfer for memory accesses with local variables in code by reorganizing variables placement.
Abstract
Resolving of memory access latency is one of the most important problems in modern embedded system design. Recently, tons of studies are presented to reduce and hide the access latency. Burst/page data transfer modes are representative hardware techniques for achieving such purpose. The burst data transfer capability offers an average access time reduction of more than 65 percent for an eight-word sequential transfer. However, solution of utilizing such burst data transfer to improve memory performance has not been accomplished at commercial level. Therefore, this paper presents a new technique that provides the maximum utilization of burst transfer for memory accesses with local variables in code by reorganizing variables placement.
참고문헌 (14)
- ARM, "CoreLink DMA Controllers", Technical reference manual, ~ (2009)
- Using DMA with high performance peripherals to maximize system performance, "J. Mangino", Texas Instrument, ~ (2007)
- Samsung, "Exynos 4 quad", technical document, ~ (2012)
- J. Barth, "Embedded DRAM design and architecture for the IBM 0.11um ASIC offering", IBM Journal of Research and Development, 46(6), pp.675~680 (2002)
- Fujitsu, "FR80S", T series DMA access speed, 2008
- STMicroelectronics, "STM DMA API", technical manual, ~ (2011)
- D. Bartely, "Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes", Software Practice & Experience, 22(2), pp.101~110 (1992)
- S. Liao, "Storage Assignment to Decrease Code Size", Proceedings on SIGPLAN Conference of PLDI, pp.186~195 (1995)
- S. Liao, "Storage Assignment to Decrease Code Size", ACM TOPLAS, 18(3), pp.235~253 (1996)
- V.K. Nandivada, "SARA: combining stack allocation and register allocation", Proceedings on International Conference on Compiler Construction, pp.232~246 (2006)
- ARM, "ARM architecture reference manual", ~ (2007)
- CACTI 3.0: an integrated cache timing, power and area model, "P. Shivakumar", HP Labs, ~ (2001)
- V. Zivojnovic, "DSPStone- A DSP oriented Benchmarking Methodology", Proceedings on International Conference of Signal Processing Applications and Technology (1994)
- C. Lee, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", Proceedings on IEEE International Symposium of Microarchitecture, pp.330~335 (1997)