FCCSP용 기판의 warpage에 미치는 설계인자와 두께편차 영향에 대한 수치적 해석
Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP
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본 논문에서는 FCCSP용 기판의 휨에 미치는 설계인자와 두께편차의 영향도를 분석하고 최적설계조건을 도출하기 위해 유한요소법에 의한 수치해석을 사용하였고 다구찌법에 의한 파라메타설계와 분산분석을 수행하였다. 해석결과에 의하면 휨에 미치는 영향은 코어재료가 가장 크고 층별 두께(솔더레지스트, 프리프레그, 회로층)의 영향도는 낮은것으로 분석되었다. 이때 솔더 레지스트와 프리프레그의 두께는 감소할수록 기판 휨은 감소하지만 회로층의 두께는 증가할수록 기판 휨이 감소하였다. 또한, 기판 휨에 대한 두께편차의 영향도 분석결과에 의하면 두께편차의 조합에 따라 기판휨은 최대 40%까지 증가하였다. 이것은 비록 개별 층의 두께편차가 기판품질 수준에 부합하더라도 두께편차 조합조건에따라 기판 휨이 크게 달라질 수 있다는 것을 의미한다. 따라서, 제조공정에서 기판 휨을 줄이기 위해서 기판두께편차는최적화되고 정밀하게 제어되어야 한다.
Abstract
In this paper, numerical analysis by finite element method, parameter design by the Taguchi method and ANOVA method were used to analyze about effect of design deviations and thickness variations on warpage of FCCSP substrate. Based on the computed results, it was known that core material in substrate was the most determining deviation for reducing warpage. Solder resist, prepreg and circuit layer were insignificant effect on warpage relatively. But these results meant not thickness effect was little importance but mechanical properties of core material were very effective. Warpage decreased as Solder resist and circuit layer thickness decreased but effect of prepreg thickness was conversely. Also, these results showed substrate warpage would be increased to maximum 40% as thickness deviation combination. It meant warpage was affected by thickness tolerance under manufacturing process even if it were met quality requirements. Threfore, it was strongly recommended that substrate thickness deviation should be optimized and controlled precisely to reduce warpage in manufacturing process.
참고문헌 (14)
- Semiconductor IC Packaging Technology Challenges:The Next Five Years, "Mario A. Bolanos", Texas Instruments, ~, pp.SPAY025
- X. J. Fan, "Design and optimization of thermo-mechanical reliability in wafer level packaging", Microelectronics Reliability, 50(4), pp.536~ (2010)
- Ming-Yi Tsi, "Investgation of thermomechanical behaviors of flip chip BGA packages during manufacuring process and thermal cycling", IEEE Trans. Compon. Pack. -Technol, 27(3), pp.568~ (2004)
- Darveaux, "Reliability of Plastic Ball Grid Array Assembly, In Ball Grid Array Technology" (1995), McGraw-Hill
- Lau, "Electronic Packaging: Design, Materials, Process, and Reliability" (1997), McGraw-Hill
- Zhang Wenge, "The effects of underfill epoxy on warpage in flip-chip assembles", IEEE Trans. Compon. Pack. Manufact. Technol - Part A, 21(2), pp.323~ (1998)
- R. Darveaux, "Interface Failure in Lead Free Solder Joints", Proc. 56th Electronic Components and Technology Conference(ECTC) (2006)
- 조승현, "Estimation of warpage and thermal stress of IVHs in flip-chip ball grid arrays package by FEM", Microelectronics and Reliability, 48(2), pp.300~309, Elsevier BV
- Lau John, "Effects of Build-Up Printed Circuit Board Thickness in the Solder Joint Reliability of a Wafer Level Chip Scale Package(WLCSP)", Trans on Components & Packaging Technologies, 25(1), pp.3~ (2002)
- Elva Lin, "Advantage and challenge of coreless Flipchip BGA Microsystems", IMPACT, pp.346~ (2007)
- Chiu Christine, "Challenges of thin core PCB Flip Chip package on advanced Si Nodes", Proc. 57th Electronic Components and Technology Conference(ECTC) (2007)
- 조승현, "New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board", MICROELECTRONICS RELIABILITY, 50, pp.242~250, PERGAMON-ELSEVIER SCIENCE LTD
- "MARC 2011 user manual", Volume A : Theory and user information, ~ (2011)
- 박성현, "현대실험계획법" (2003), 민영사