단면 연마된 실리콘 웨이퍼의 열에 의한 휨 거동
Thermal Warpage Behavior of Single-Side Polished Silicon Wafers
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초록
반도체 패키지의 경박단소화로 인해 발생하는 복잡한 휨 거동은 내부 응력을 발생시켜 박리나 균열과 같은 다양한 기계적인 결함을 야기한다. 이에 따른 수율 감소를 막기 위해 휨 거동을 정확하게 예측하려는 노력은 다양한 측면에서 그 접근이 이루어지고 있다. 이 중 패키지를 구성하는 주 재료인 실리콘 웨이퍼는 일반적으로 균질한 물질로 취급되어 열에 의한 휨 거동은 전혀 없는 것으로 묘사된다. 그러나 실리콘을 얇게 가공하기 위해서 진행되는 그라인딩과 폴리싱에 의해 상온에서 휨이 발생한다는 사실이 보고되어 있고, 이는 표면에 형성되는 damage layer가 두께 방향으로 불균질함을 발생시키는 것으로부터 기인한다. 이에 본 논문에서는 반도체 패키징 공정 중 최고온 공정 과정인 solder reflow 온도에서 단면 연마된 웨이퍼가 나타내는 휨 거동을 측정하고, 이러한 휨 량이 나타나는 원인을 연마된 면과 그렇지 않은 면의 열팽창계수를 측정함으로써 밝혀내었다. 측정에는 미세 변형률과 형상이 모두 측정 가능한 3차원 디지털 이미지상관법(Digital Image Correlation; DIC)을 이용하였다.
Abstract
Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.
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