PERC 태양전지에서 반사방지막과 p-n 접합 사이에 삽입된 SiOx 층의 두께가 Potential-Induced Degradation (PID) 저감에 미치는 영향
Thickness Effect of SiOx Layer Inserted between Anti-Reflection Coating and p-n Junction on Potential-Induced Degradation (PID) of PERC Solar Cells
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친환경 및 고효율의 장점 때문에 신재생 에너지원으로 널리 사용되고 있는 실리콘 태양 전지는 모듈을 직렬연결하여 발전할 때 500-1,500 V의 전압이 걸리게 된다. 모듈 프레임과 태양 전지 사이에 걸린 이러한 고전압 차에 의해장시간 가동시 효율 및 최대 출력이 감소하는 현상인 potential-induced degradation(PID)은 실리콘 태양 전지의 수명을단축시키는 주요 원인 중 하나로 알려져 있다. 특별히 전면 유리의 Na+ 이온이 고전압에 의해 반사방지막을 거쳐 실리콘내부로 확산하여 실리콘 내부 적층 결함 등에 축적되는 것이 PID의 원인으로 보고되고 있다. 본 연구에서는 p-형 PERC (passivated emitter and rear contact) 구조 실리콘 태양전지를 대상으로 Na+ 이온의 확산 장벽으로 작용할 수 있는 SiOx 층이 p-n 접합과 반사방지막 사이에 삽입되었을 때 그 두께가 PID 현상 완화에 미치는 영향을 연구하였다. 96 시간 동안1,000 V의 전압을 연속적으로 가한 후 병렬 저항, 효율 및 최대 출력을 측정한 결과 삽입된 SiOx 장벽층의 두께가 7-8 nm 이상일 때 비로소 PID 현상이 효과적으로 완화되는 것으로 나타났다.
Abstract
Silicon solar cells have been widely used as a most promising renewable energy source due to eco-friendliness and high efficiency. As modules of silicon solar cells are connected in series for a practical electricity generation, a large voltage of 500-1,500 V is applied to the modules inevitably. Potential-induced degradation (PID), a deterioration of the efficiency and maximum power output by the continuously applied high voltage between the module frames and solar cells, has been regarded as the major cause that reduces the lifetime of silicon solar cells. In particular, the migration of the Na+ ions from the front glass into Si through the anti-reflection coating and the accumulation of Na+ ions at stacking faults inside Si have been reported as the reason of PID. In this research, the thickness effect of SiOx layer that can block the migration of Na+ ions on the reduction of PID is investigated as it is incorporated between anti-reflection coating and p-n junction in p-type PERC solar cells. From the measurement of shunt resistance, efficiency, and maximum power output after the continuous application of 1,000 V for 96 hours, it is revealed that the thickness of SiOx layer should be larger than 7-8 nm to reduce PID effectively.
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