전기화학적 도금을 이용한 wrap-around 게이트 나노구조의 제작
Fabrication of wrap-around gate nanostructures from electrochemical deposition
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초록
Wrap-around 전계효과 트랜지스터는 채널과 전극간의 커플링을 매우 커서 채널길이가 짧아지면서 생기는 단채널효과(short channel effect)를 개선시킬 수 있는 이유로 많은 관심을 불러왔다. 본 논문에서는 실리콘 나노와이어를 이용하여 상향식의 wrap-around 전계효과 트랜지스터(FET)의 제작 공정을 소개한다. 소자의 제작 공정은 크게 전자빔 리소그래피, 유전영동(dielectrophoresis)을 이용한 나노와이어의 효과적 정렬 그리고 게이트 전극의 전기 화학적 도금(electrochemical deposition)을 이용한 생성 등의 방법들로 이루어진다. 전기 화학적 도금을 위한 용액은 독성을 띄지 않는 유기물 용액을 사용하였다. 액체 질소를 이용하여 polymethyl methacrylate(PMMA)가 전기화학적 도금시 형태를 잃지 않게 함으로써, 패터닝된 PMMA가 wrap-around 게이트 나노구조를 제작하기 위한 나노 템플릿으로 사용될 수 있도록 하였다.
Abstract
To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.
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