소형 애플리케이션에 적합한 AES-128 기반 저면적 암호화 회로 설계
Design of Low-area Encryption Circuit Based on AES-128 Suitable for Tiny Applications
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초록
정보화 기술의 발전에 따라 웨어러블 장치, 휴대용 장치, RFID와 같은 소형 애플리케이션에 대한 관심이 증가하고 있고, 여기에 적용하기 위한 소형 암호화 회로의 중요성이 강조되고 있다. 본 논문에서는 소형 애플리케이션에 적합한 AES 기반 암호화 회로를 제안한다. 제안하는 회로에서는 저장 공간의 최소화, 연산 자원의 공유를 통해서 크기를 최소화 하였다. 제안하는 회로는 8x16 비트 크기의 SRAM 두 개를 사용하였으며, 65nm 표준 셀 라이브러리를 이용하여 합성한 결과 2,241 개의 게이트로 구현되었고, 처리 속도는 초당 50.57M 비트이다. 따라서 저면적 암호화 회로를 필요로 하는 다양한 애플리케이션에 적용하여 사용할 수 있다.
Abstract
As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two 8x16-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.
참고문헌 (10)
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