블록 기반 압축 이미지 및 비디오를 위한디블로킹 필터의 SoC 구현
SoC Implementation of Deblocking Filter for Block-based Compressed Images and Videos
2
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
본 논문에서는 Zynq Soc Platform의 부분 재구성 기능을 사용하여 영상 압축으로 생성된 blocking artifacts를 제거하는후처리 시스템을 설계한다. 높은 연산량을 제공하고 실시간으로 1080p 영상을 처리하도록 부분 재구성이 가능한 FPGA(Field Programmable Gate Array) 영역에 디블로킹 필터를 구현한다. 또한 부분적으로 재구성 가능한 영역을 활용하여 제한된 환경의 임베디드 시스템에서 하드웨어 리소스를 보다 효율적으로 사용할 수 있다. 제안된 시스템의 실험결과는 디블로킹필터처리 후 약 0.6dB의 PSNR 향상을 보여준다. Zynq SoC에서 구현된 필터가 동작할 때 68.33mW의 전력을 소모한다.
Abstract
In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to removeblocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a FieldProgrammable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently inhighly resource-constrained embedded systems. Experimental results of the proposed system show improvement ofvisual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measuredpower consumption of the deblocking filter during run-time is 68.33mW.
참고문헌 (14)
- Nelson C. Francisco, "A generic post-deblocking filter for block based image compression algorithms", Signal Processing: Image Communication, 27(9), pp.985~997 (2012), Elsevier BV[DOI]
- Gwangseok Seo, "Implementation of Deblocking Filter Using Partial Reconfiguration on FPGA", KOREA INFORMATION SCIENCE SOCIETY, pp.1010~1012 (2017)
- "DS190(v1.11), Zynq-7000 All Programmable SoC Data Sheet：Overview", Xilinx, ~ (2017)
- Joao Silva, "Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip", IEEE Embedded Systems Letters, 7(1), pp.31~34 (2015), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- "UG585(v1.11), Zynq-7000 All Programmable SoC Technical Reference Manual", Xilinx, ~ (2016)
- "WP374(v1.2) “Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite”", Xilinx, ~ (2012)
- "UG909(v2015.1), Vivado Design Suite User Guide Partial Reconfiguration,” Xilinx", Xilinx, ~ (2015)
- "XAPP1231(v1.1), Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite for Zynq-7000 AP SoC Processor", Xilinx, ~ (2015)
- "WP416(v1.1), Vivado Design Suite", Xilinx, ~ (2012)
- A. Cortes, "High level synthesis using Vivado HLS for Zynq SoC : Image processing case studies", Design of Circuits and Integrated Systems (DCIS) (2016)
- M. Fingeroff, "High-Level Synthesis Blue Book" (2010), Mentor Graphics Corp.
- Sung Deuk Kim, "A deblocking filter with two separate modes in block-based video coding", IEEE Transactions on Circuits and Systems for Video Technology, 9(1), pp.156~160 (1999), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- "PG307, AXI Performance Monitor v5.0", Xilinx, ~ (2016)
- "UCD9248, Digital PWM System Controller", Texas Instruments, ~ (2012)