A software-controlled bandwidth allocation scheme for multiple router on-chip-networks
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As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included inon-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitrationresult by combining multiple routers. Allocating desired bandwidths to the ports across the routers is moredifficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed toovercome the limitations of existing local arbitration policies. Each IP can control the priority of a packetdepending on the data communication requirement within the allocated bandwidth. The experimental resultsshow that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple routeron-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.
Abstract
As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included inon-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitrationresult by combining multiple routers. Allocating desired bandwidths to the ports across the routers is moredifficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed toovercome the limitations of existing local arbitration policies. Each IP can control the priority of a packetdepending on the data communication requirement within the allocated bandwidth. The experimental resultsshow that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple routeron-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.
참고문헌 (5)
- 이상헌, "다중 채널과 동시 라우팅 기능을 갖는고성능 SoC 온 칩 버스 구조", 전자공학회논문지 - SD, 44(4), pp.24~31 (2007), 대한전자공학회
- Chi-Ming Chung, "A comparative analysis of different arbitration protocols for multiple-bus multiprocessors", Journal of Computer Science and Technology, 11(3), pp.313~325 (1996), Springer Science and Business Media LLC[DOI]
- K. Lahiri, "The LOTTERYBUS on-chip communication architecture", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(6), pp.596~608 (2006), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- ARM, "AMBA AXI Specification, Revision 2.0", ~ (2010)
- 이찬호, "효율적인 네트워크 사용을 위한 온 칩 네트워크 프로토콜", 전자공학회논문지 - SD, 47(1), pp.86~93 (2010), 대한전자공학회