딥러닝을 하드웨어 가속기를 위한 저전력 BSPE Core 구현
Implementation of low power BSPE Core for deep learning hardware accelerators
0
조회
0
다운로드
1
인용
0
참고문헌
키워드
초록
본 논문에서 BSPE는 전력이 많이 소모되는 기존의 곱셈 알고리즘을 대체했다. Bit-serial Multiplier를 이용해 하드웨어 자원을 줄였으며, 메모리 사용량을 줄이기 위해 가변적인 정수 형태의 데이터를 사용한다. 또한, 부분 합을 더하는 MOA(MultiOperand Adder)에 LOA(Lower-part OR Approximation)를 적용해서 MOA의 자원 사용량 및 전력사용량을 줄였다. 따라서기존 MBS(Multiplication by Barrel Shifter)보다 하드웨어 자원과 전력이 각각 44%와 42%가 감소했다. 또한, BSPE Core를위한 hardware architecture design을 제안한다.
Abstract
In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resourcesare reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOAresource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (MultiOperand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter),hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardwarearchitecture design for BSPE Core.
참고문헌 (12)
- C. W. Cho, "Low power for deep learning hardware accelerators Bit-Serial Multiplier based Processing Element", IKEEE Conference (2020)
- C. W. Cho, "Bit-Serial multiplier based Neural Processing Element with Approximate adder tree", International SoC Design Conference (ISOCC) (2020)
- Mahdiani, Hamid Reza, "Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications", IEEE Transactions on Circuits and Systems I:Regular Papers, 57(4), pp.850~862 (2009)[DOI]
- Abdelouahab, Kamel, "The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it!", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.157~160 (2018)
- Chen, Tianshi, "Diannao: A small-footprint high-throughput accelerator for ubiquitous machinelearning", ACM SIGARCH Computer Architecture News, 42(1), pp.269~284 (2014)[DOI]
- Chen, Yu-Hsin, "Eyeriss: An energyefficient reconfigurable accelerator for deep convolutional neural networks", IEEE journal of solidstate circuits, 52(1), pp.127~138 (2016)[DOI]
- Jouppi, Norman P., "In-datacenter performance analysis of a tensor processing unit", Proceedings of the 44th Annual International Symposium on Computer Architecture, 45(2) (2017)
- Lee, Jinmook, "UNPU: A 50.6 TOPS", W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision, 2018 (2018), ~[DOI]
- Abdelouahab, Kamel, "The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it!", Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.157~160 (2018)
- Park, Hyunbin, "Digital Neuron: A Hardware Inference Accelerator for Convolutional Deep Neural Networks", arXiv preprint arXiv:1812.07517, ~ (2018)
- Sharma, Hardik, "Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network", 2018 ACM, 2018, ~[DOI]
- Alwani, Manoj, "Fused-layer CNN accelerators", 2016 49th Annual IEEE, 2016, ~[DOI]