SHA-3 해시 함수의 최적화된 하드웨어 구현
An Optimized Hardware Implementation of SHA-3 Hash Functions
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초록
본 논문에서는 NIST에서 발표한 Secure Hash Algorithm (SHA) 표준의 최신 버전인 SHA-3 해시 함수의 하드웨어 구현과 함께 보안 SoC 응용을 위한 ARM Cortex-M0 인터페이스 구현에 대해 기술한다. 최적화된 설계를 위해 5 가지 하드웨어구조에 대해 하드웨어 복잡도와 성능의 교환조건을 분석하였으며, 분석 결과를 토대로 라운드 블록의 데이터패스를 1600-비트로 결정하였다. 또한, 라운드 블록과 64-비트 인터페이스를 갖는 패더를 하드웨어로 구현하였다. SHA-3 해시 프로세서,Cortex-M0 그리고 AHB 인터페이스를 집적하는 SoC 프로토타입을 Cyclone-V FPGA 디바이스에 구현하여 하드웨어/소프트웨어 통합 검증을 수행하였다. SHA-3 프로세서는 Virtex-5 FPGA에서 1,672 슬라이스를 사용하였으며, 최대 289 Mhz의클록 주파수로 동작하여 5.04 Gbps의 처리율을 갖는 것으로 예측되었다.
Abstract
This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latestversion of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface forsecurity SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performancewas analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on thebasis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented inCyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of5.04 Gbps.
참고문헌 (14)
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