CAN-FD 프로토콜에서 신뢰성과 보안성이 향상된인증된 암호화 아키텍쳐 및 하드웨어 엔진의 설계
Design of a Authenticated Encryption Architecure and Hardware Engine with Improved Reliability and Security on CAN-FD Protocol
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초록
본 논문에서는 CAN-FD 프로토콜에서 인증된 암호화의 신뢰성과 보안성을 향상시키기 위한 아키텍쳐를 제안하고 이를 하드웨어로 구현하였다. 제안된 아키텍쳐는 병렬 처리에 용이하도록 AES-128과 HMAC에 기반한 Encrypt-and-MAC 방식을 사용하였으며신뢰성을 향상시키기 위해 하드웨어 이중화를 적용했다. 또한 채널 간 전송 횟수를 기억하는 카운터를 도입하여 마치 추가 암호 키처럼 사용하여 하드웨어 부담을 최소화하면서도 보안성을 강화하였다. 제안된 아키텍쳐를 위한 하드웨어 엔진을 FPGA로 설계하고,CAN-FD 버스 상에서 동작하는 것을 확인하였다.
Abstract
In this paper, an authenticated encryption architecture with improved reliability and security is proposed andimplemented in hardware. The proposed architecture exploits Encrypt-and-MAC based on AES-128 and HMAC foreasy parallelization. It exploits dual modular redundancy to improve reliability. It also exploits channel communicationcounter as additional encryption key, so security is improved with minimum additional hardware cost. Hardwareengine of the proposed architecture was designed in FPGA, and it was verified to work correctly on CAN-FD bus.
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